1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly, to a semiconductor integrated circuit device including a MOS (Metal-Oxide-Semiconductor) transistor whose source and drain regions have equivalent resistances, respectively.
2.Description of the Related Art
A semiconductor integrated circuit device usually includes a Complementary MOS (CMOS) inverter, which is composed of a p-channel MOS transistor and an n-channel MOS transistor connected in series. The source region of the p-channel MOS transistor is electrically connected to a wiring layer (power supply wiring layer) to be connected to a power supply, the drain region thereof is electrically connected to a wiring layer (output wiring layer) from which an output signal is taken out and the drain region of the n-channel MOS transistor, and the source region of the n-channel MOS transistor is electrically connected to a wiring layer (ground wiring layer) to be grounded.
Conventionally, metal layers having low electrical resistivities, such as aluminum and its alloys, are widely used as the wiring layers, and these metal layers are directly contact with the source regions and the drain regions, respectively, for interconnection.
With conventional semiconductor integrated circuit devices, when the CMOS inverter is directly connected to an input terminal or pin and/or an output terminal or pin of the integrated circuit device, the source and drain regions of the transistor are electrically connected to the metal wiring layers through wiring layers made of a material other than metal in order to prevent its breakdown due to electrostatic pulses. The entire contacting area of the source and drain regions are respectively contacted with the wiring layers made of material other than metal. Thus, alloy spiking due to electrostatic pulses can be prevented.
In addition, in order to increase the electrostatic discharge withstanding voltage circuit configurations and/or layouts of input and output protection circuits are devised, and the input and/or output terminals or pins used are suitably selected.
However, with conventional semiconductor integrated circuit devices, even if the above-described protection means is provided, there is a problem in that when electrostatic pulses are applied between the power supply terminal and the ground terminal of the device, some of the source and drain regions and the gate insulators of the n- and/or p-channel MOS transistor constituting the CMOS inverter are destroyed in an internal circuit of the device. Here, the word "internal circuit" means a circuit where all transistors in its internal circuit are not directly connected to the external terminals or pins of the integrated circuit device.
The above-described problem is particularly important for a comparatively large MOS transistor having a channel width of 100 .mu.m or more. It is believed that the problem results from the fact that an internal electric resistance of such a transistor is comparatively low so that most of the electric current due to the electrostatic pulses flows through the transistor.
There are some measures available to solve the problem, one of which is to respectively provide protection resistors, such as diffusion resistors, to the power supply wiring layer and the ground wiring layer. However, there arises the problem that high-speed operation of the transistor is degraded because large electric resistances are respectively inserted in the power supply and ground wiring layers in series.
Another available measure is that internal resistances existing in the source and drain regions of the MOS transistor are utilized as protection resistors. This measure is often employed in an output transistor, in which distances between the contact areas of the source and drain regions from the metal wiring layers and the gate electrode are set longer than the standard values. However, there arises the problem of an increase in pellet-size because the chip-occupied area of the transistor becomes large.